Design of cost-Efficient interconnect processing units : spidergon STNoC / Marcello Coppola [et al.] [Electronic book]

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Title	Design of cost-Efficient interconnect processing units : spidergon STNoC / Marcello Coppola [et al.] [Electronic book]
LC Call #	TK5105.546 C67 2009
Author	Coppola, Marcello
Added Author	Grammatikakis, Miltos D.
	Locatelli, Riccardo
	Maruccia, Giuseppe
	Pieralisis, Lorenzo
Content	Towards Multicores: Technology and Software Complexity
	On-Chip Bus vs. Network-on-Chip
	NoC Topology
	The Spidergon STNoC
	SoC and NoC Design Methodology and Tools
	Conclusions and Future Work
Subject	Networks on a chip
	Microprocessors
ISBN	978-1-4200-4471-3 (hardback :alk.paper)
Published/Created	Boca Raton, Fl. : CRC Press, 2009.
Links	https://thailandconsortium.crcnetbase.com/books/7118/44710_c000.pdf

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